1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device, and more particularly, to a test circuit for reading data of a non-volatile semiconductor memory element.
2. Description of the Related Art
FIG. 5 illustrates a related-art non-volatile memory element data write/read circuit. The related-art non-volatile memory element data write/read circuit includes a PMOS one-time programming (OTP) element 500 as an example of a non-volatile memory element. The PMOS OTP element 500 has a source terminal connected to a drain terminal of a PMOS transistor 530. The PMOS transistor 530 has a source terminal connected to a high voltage side power supply terminal VDD. A read circuit 510 includes a PMOS transistor 511, an NMOS transistor 512, and a latch 513. A data output terminal DOUT is connected to an input/output terminal of the latch 513, a drain terminal of the PMOS transistor 511, and a drain terminal of the NMOS transistor 512. The NMOS transistor 512 has a source terminal connected to a low voltage side power supply terminal VSS. The PMOS transistor 511 has a source terminal connected to a drain terminal of the PMOS OTP element 500. A write circuit 520 includes a PMOS transistor 521 and a written data transmission circuit 522.
The written data transmission circuit 522 has an output terminal WDATAX connected to a drain terminal of the PMOS transistor 521. The PMOS transistor 521 has a source terminal connected to the drain terminal of the PMOS OTP element 500. A control circuit 540 outputs a signal RENX, a signal WENX, a signal MEMX, and a signal CLR to a gate terminal of the PMOS transistor 511, a gate terminal of the PMOS transistor 521, a gate terminal of the PMOS transistor 530, and a gate terminal of the NMOS transistor 512, respectively, in accordance with a read mode signal φ1 or a write mode signal φ2 to be set.
Next, a description is given of the circuit operation.
(Writing of Data 1 into OTP Element)
FIG. 6A shows a timing chart of the respective signals in the case of writing data 1 into the PMOS OTP element 500. When a write mode is set, the write mode signal φ2 becomes “High”. In a period of t<t1, the gate terminal RENX of the PMOS transistor 511 is level “High” and in the OFF state, the gate terminal CLR of the NMOS transistor 512 is level “Low” and in the OFF state, the gate terminal WENX of the PMOS transistor 521 is level “High” and in the OFF state, and the gate terminal MEMX of the PMOS transistor 530 is level “Low” and in the ON state. The output of the written data transmission circuit 522 is indefinite. In a period of t1<t<t2, the written data transmission circuit 522 outputs level “Low”, and WDATAX becomes level “Low”. In a period of t2<t<t3, WENX is set to level “Low” to turn on the PMOS transistor 521. In response thereto, level “Low” is transmitted to the drain terminal of the PMOS OTP element 500. In a period of t3<t<t4, by applying a write voltage VPP level to the VDD terminal, VPP is applied between the drain and source of the PMOS OTP element 500, to thereby write data 1. When data 1 is written, the PMOS OTP element 500 becomes a conductive state.
(Writing of Data 0 into OTP Element)
FIG. 6B shows a timing chart of the respective signals in the case of writing data 0 into the PMOS OTP element 500. When the write mode is set, the write mode signal φ2 becomes “High”. The operation in the period of t<t1 is the same as that in the case of writing of data 1. In the period of t1<t<t2, the written data transmission circuit 522 outputs level “High”, and WDATAX becomes level “High”. In the period of t2<t<t3, WENX is set to level “Low” to turn on the PMOS transistor 521. In response thereto, level “High” is transmitted to the drain terminal of the PMOS OTP element 500. In the period of t3<t<t4, the write voltage VPP level is applied to the VDD terminal. A potential difference between the drain and source of the PMOS OTP element 500, however, 0 V, and thus data 1 is not written. When data 1 is written, the PMOS OTP element 500 becomes a conductive state. In other words, the PMOS OTP element 500 remains in a non-conductive state, and hence maintains data 0.
(Reading of Data 1 from OTP Element)
FIG. 7A shows a timing chart of the respective signals in the case of reading data 1 from the PMOS OTP element 500. When a read mode is set, the read mode signal φ1 becomes “High”. In the period of t<t1, the gate terminal RENX of the PMOS transistor 511 is level “High”, the gate terminal CLR of the NMOS transistor 512 is level “Low”, the gate terminal WENX of the PMOS transistor 521 is level “High”, and the gate terminal MEMX of the PMOS transistor 530 is level “High”, and hence the respective switches are all turned off. The potential of the data output terminal DOUT is at the level of previous read data held by the latch 513. In the period of t1<t<t2, CLR is set to level “High” to turn on the NMOS transistor 512, to thereby set the data output terminal DOUT to level “Low”. In the period of t2<t<t3, CLR is set to level “Low” to turn off the NMOS transistor 512, but the data output terminal DOUT still maintains level “Low” due to the operation of the latch 513. In the period of t3<t<t4, RENX is set to level “Low” and MEMX is set to level “Low” to turn on the PMOS transistor 511 and the PMOS transistor 530. In this case, the PMOS OTP element 500 is in the conductive state (data 1 is stored), and hence the data output terminal DOUT is pulled up to level “High”. In the period of t>t4, RENX is set to level “High” and MEMX is set to level “High” to turn off the PMOS transistor 511 and the PMOS transistor 530, but the data output terminal DOUT still maintains level “High” due to the operation of the latch 513. Through the operation described above, data 1 is read.
(Reading of Data 0 from OTP Element)
FIG. 7B shows a timing chart of the respective signals in the case of reading data 0 from the PMOS OTP element 500. When the read mode is set, the read mode signal φ1 becomes “High”. The operation in the period of t<t3 is the same as that in the case of reading of data 1. In the period of t3<t<t4, RENX is set to level “Low” and MEMX is set to level “Low” to turn on the PMOS transistor 511 and the PMOS transistor 530. In this case, the PMOS OTP element 500 is in the non-conductive state (data 0 is stored), and hence the data output terminal DOUT cannot be pulled up to level “High” but remains level “Low”. In the period of t>t4, RENX is set to level “High” and MEMX is set to level “High” to turn off the PMOS transistor 511 and the PMOS transistor 530, but the data output terminal DOUT still maintains level “Low” due to the operation of the latch 513. Through the operation described above, data 0 is read (see, for example, Japanese Patent Application Laid-open No. 2010-192039).
Examples of use of the circuit of FIG. 5 include the application of trimming for a voltage value of a constant voltage circuit as illustrated in FIG. 8. The constant voltage circuit includes a reference voltage circuit 801, an amplifier 802, an output transistor 803, and a resistor circuit 804 including a trimming circuit. Data output terminals DOUT1 to DOUTn of a plurality of the non-volatile memory element data write/read circuits illustrated in FIG. 5 are connected to input terminals of the resistor circuit 804 of FIG. 8. Initial measurement is performed before trimming. Then, a trimming amount is determined by a calculating formula based on the result of the measurement, and data is written into the non-volatile memory element.
In the related-art non-volatile memory element data write/read circuit, however, in the case where trimming for the constant voltage circuit or the like is performed by using data of the non-volatile memory element, there is a problem in that the accuracy of trimming is poor because of fluctuations in resistor circuit ratio and fluctuations in peripheral circuits.